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<div class="title">csi2txss Documentation</div>  </div>
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<div class="textblock"><p>This is main header file of the Xilinx MIPI CSI Tx Subsystem driver. <b>MIPI CSI2 Tx Subsystem Overview</b></p>
<p>CSI-2 Tx Controller receives stream of image data via Native / AXI4 Stream input interface. It Packs the incoming image data into CSI-2 Packet Structure i.e Packs the Synchronization pacckets &amp; performs the pixel-2-Byte Conversions for the pixel Data.Packed Byte data is sent over the D-PHY Interface for transmission. AXI4-Lite interface will be used to access core registers. CSI2-Tx Controller support’s ECC &amp; CRC generation for header &amp; payload respectively.</p>
<p><b>Core Features</b> The Xilinx CSI-2 Tx Subsystem has the following features: • Compliant with the MIPI CSI-2 Interface Specification, rev. 1.1 • Standard PPI interface i.e. D-PHY • 1-4 Lane Support,configurable through GUI • Maximum Data Rate per – 1.5 Gigabits per second • Multiple data type support : o RAW8,RAW10,RAW12,RAW14,RGB888,YUV422-8Bit,User defined Data types • Supports Single,Dual,Quad Pixel Modes, configurable through GUI • Virtual channel Support (1 to 4) • Low Power State(LPS) insertion between the packets. • Ultra Low Power(ULP) mode generation using register access. • Interrupt generation &amp; Core Status information can be accessed through Register Interface • Multilane interoperability. • ECC generation for packet header. • CRC generation for data bytes(Can be Enabled / Disabled), configurable through GUI. • Pixel byte conversion based on data format. • AXI4-Lite interface to access core registers. • Compliant with Xilinx AXI Stream Interface &amp; native Interface for input video stream. • LS/LE Packet Generation,can be configured through register interface. • Configurable selection of D-PHY Register Interface through GUI options. • Support for transmission of Embedded Data packet’s through Input Interface.</p>
<p><b>Software Initialization &amp; Configuration</b></p>
<p>The application needs to do following steps in order for preparing the MIPI CSI2 Tx Subsystem core to be ready.</p>
<ul>
<li>Call XCsi2TxSs_LookupConfig using a device ID to find the core configuration.</li>
<li>Call XCsi2TxSs_CfgInitialize to initialize the device and the driver instance associated with it.</li>
</ul>
<p><b>Interrupts</b></p>
<p>The <a class="el" href="group__csi2txss.html#ga445feeebfebea8ae0119be48a4a27ede" title="This routine installs an asynchronous callback function for the given HandlerType: ...">XCsi2TxSs_SetCallBack()</a> is used to register the call back functions for MIPI CSI2 Tx Subsystem driver with the corresponding handles</p>
<p><b> Virtual Memory </b></p>
<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
<p><b> Threads </b></p>
<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
<p><b>Asserts</b></p>
<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that application developers leave asserts on during development.</p>
<p><b>Building the driver</b></p>
<p>The MIPI CSI2 Tx Subsystem driver is composed of source files and depends on the CSI and DPHY drivers. The DPHY driver is pulled in only if the register interface has been enabled for it.Otherwise the CSI2TX driver and subsystem files are built.</p>
<pre>
  MODIFICATION HISTORY:</pre><pre>  Ver Who  Date     Changes
</p>
<hr/>
<p>
  1.0 sss 07/14/16 Initial release
      ms  01/23/17 Modified xil_printf statement in main function for all
                   examples to ensure that "Successfully ran" and "Failed"
                   strings are available in all examples. This is a fix
                   for CR-965028.
      ms  03/17/17 Added readme.txt file in examples folder for doxygen
                   generation.
      vsa 15/12/17 Add support for Clock Mode
  1.2 vsa 02/28/18 Add Frame End Generation feature
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